Documentation about the Serial Peripheral Interface (SPI)

I share here information about the Serial Peripheral Interface (SPI). These might be useful to other people who have similar requirements.

Introduction

The SPI master controls the SPI data exchange using two signals

SCK: the SPI clock signal
NSS: the slave select signal which is by convention active low

The master outputs the MOSI signal, which is usually always active (not tri-state). If there are multiple slaves, MOSI is connected to all slave input pins.

The master has a MISO input pin. If there are multiple slaves, then usually all slave output (SO) pins are wired together to the MISO pin. This requires that the SO pins are tri-state outputs, which are enabled when a chip select (NCS) input pin at the slave is asserted.

There can be special, unexpected behaviour: MMC and SD cards do have NCS pins and tri-state SO pins, but it is documented that their SO does not immediately go tri-state when NCS is deasserted, but rather the MMC or SD card needs some more SCK cycles before they tri-state SO. This can lead to problems when other SPI devices share the same bus with a MMC or SD card. A hardware solution to this issue is to put an additional 1/4 74HC125 or 74HCT125 gate between SO and MISO. If the micro-controller runs with +5 V, then 1/4 74HCT125 is anyway needed to bring the MMC/SDC SO signal from +3.3 V to +5 V.

My Use Cases

My SPI use cases so far:

Microchip 25LC1024 EEPROM
Various MMC & SD cards
Microchip ENC28J60

All three use SPI "Mode 0", which is CPOL=0 and CPHA=0 in the AVR micro-controller documentation. In all the cases the most significant bit (MSb) comes first.

But what is the difference between the SPI modes?

About the SPI Modes

While the SPI is always conceptionally shown as two connected 8-bit shift registers, this is an over simplification. The main issue with two coupled 8-bit shift registers is additional delay on the clock line, which could cause the communication to not work, because data would be sampled too late. This is critical because the allowed additional delays must be below the D-flip-flip clock to output delay, which are in the oder of nanoseconds with today's technology.

The SPI solution to this is to decouple sending and receiving by using both clock edges. Conceptually, this can be visualised as one 8-bit shift register sending the data i.e. driving a master's MOSI pin and another one reading the master's MISO pin. The two shift registers are driven by opposite clock edges. The "clock phase" (CPHA) mode selects whether the receiving or sending 8-bit shift register goes first.

This can be implemented in hardware using fewer devices than two shift registers, with the same effect. For example using one 8-bit shift register plus a 1-bit latch that delays MOSI by half a clock cycle.

Exposing externally the clock signal or the inverted clock signal is the second degree of freedom (CPOL), which brings the number of modes to four.

Note that the same technique needs to be employed on the slave side. Obviously, the master and slave modes need to be aligned.

Usually the slave mode is fixed in hardware and the master mode needs to be set to match the slave's. This could create issues when a master needs to support multiple slaves with different modes, because switching modes on the fly could for example create unwanted clock edges et cetera.

Timing Diagram for CPOL=0, CPHA=0

CPOL=0, CPHA=0 means that

the master samples SI at the rising edge of SCK
the master's MO changes shortly after the rising edge of SCK
the slave samples SO at the falling edge of SCK
the slave's SO changes shortly after the falling edge of SCK

Graphically:

                      _________           _________           ________
SCK  ________________/         \_________/         \_________/        \________ ...   \__________

                               |tdm|               |tdm|              |tdm|
     ______________________________ ___________________ __________________ ____     __________
MOSI XXXXX__MSb=bit7_______________X___bit6____________X___bit5___________X____ ... __________


                               |tds |              |tds |             |tds |
           _________________________ ____________________ _________________ ___     __________
MISO------<_MSb=bit7________________X__bit6______________X__bit5___________X___ ... __________>---


       |te|
     __                                                                                    ____
NCS    \_______________________________________________________________________ ... ______/

Timing in nanoseconds

	min.	typ.	max.
tdm	22	25	27